Federal Communications Commission (FCC) has allotted a spectrum of bandwidth in the 60 GHz frequency range (57 to 64 GHz). The Wireless Gigabit Alliance (WiGig) is targeting the standardization of this frequency band that will support data transmission rates up to 7 Gbps. Integrated circuits, formed in semiconductor die, offer high frequency operation in this millimeter wavelength range of frequencies. Some of these integrated circuits utilize Complementary Metal Oxide Semiconductor (CMOS), Silicon-Germanium (SiGe) or GaAs (Gallium Arsenide) technology to form the dice in these designs. The receive path of the signal being transferred in the wireless channel in these communication system need to be compensated for various very dispersive conditions occurring in the wireless channel. Some of these conditions include multipath reflection, multipath resilience, ISI (Inter Symbol Interference), channel capacity, strategies for frequency diversity scheduling, etc. This standard is called the IEEE 802.11 ad protocol.
CMOS (Complementary Metal Oxide Semiconductor) is the primary technology used to construct integrated circuits. N-channel devices and P-channel devices (MOS device) are used in this technology which uses fine line technology to consistently reduce the channel length of the MOS devices. Current channel lengths are 40 nm, the power supply of VDD equals 1.2V and the number of layers of metal levels can be 8 or more.
CMOS offers the computing power to perform many of the required compensation techniques requires overcoming the adverse conditions of the wireless channel. Yet, the computing power must be used in a power efficient manner to insure that the dissipated power is low enough to allow these important building blocks of the transceiver fabricated in CMOS to be used in mobile applications. This helps to insure that the energy drawn from the limited power contained in the battery is minimized while achieving the optimum performance.
Orthogonal frequency division multiplexing (OFMA) is a multi-carrier system that has been used in various communication Standards such as 802.11 (Wi-Fi), digital video broadcasting (DVB), asymmetrical digital subscriber lines (ASDL), etc. However, OFDM suffers from several deficiencies including peak to average power ratio (PAPR), sensitivity to amplifier nonlinearities, and effects of frequency offsets. Single carrier (SC) communication systems, however, overcome these several deficiencies and offer several benefits over OFDM systems.
SC communication systems is a single-carrier transmit signal that partitions their wideband channel into a large number of parallel narrowband subcarriers and has a lower PAPR resulting in design parameters in the transmit path that are simpler to achieve when compared to OFDM.
The block diagram 1-1 represents a digital radio baseband system coupled to an RF transceiver as illustrated in FIG. 1A. The input signals are mapped 1-2 into symbols, then the symbols are converted from a serial path into parallel blocks with a series to parallel (S/P) converter 1-3 so a cyclic prefix 1-4 can be added to each block. A parallel to serial (P/S) converter 1-5 recombines these blocks into a serial link which is zero padded and filtered 1-6. A digital to analog (D/A) converter 1-7 converts the digital serial link to an analog signal and presented to an analog transmitter 1-8. The signal is sent over the wireless channel 1-9 which time disperses the signal and introduces noise 1-21 into the signal. A receiver front end 1-10 receives and converts the distorted wireless signal to a digital signal with an analog to digital (A/D) converter 1-11. The signal is then filtered 1-12. The prefix is removed 1-13 and a S/P converter 1-14 generates a time domain of parallel block signals that are converter by an fast Fourier transform (FFT) 1-15 in to the frequency domain. A frequency domain equalizer 1-16 is applied to each of the transmitted subcarriers where the channel distortion caused by the channel is compensated for each subcarrier by the frequency domain equalizer. The FFT and frequency domain equalization requires less computation power than an equivalent performing time-domain equalization. An inverse FFT (IFFT) 1-17 generates the time domain representation of the frequency compensated transmitted signal to a de-mapper unit 1-18 after which the signal is applied to a P/S converter 1-19. The output signal is applied to the baseband circuitry of the receiver to extract the signals from the transmitter. The combination of the FFT, FDE and IFFT is contained within the dotted box 1-20 and will be described in more detail shortly.
In the block diagram 1-21 as illustrated in FIG. 1B, the input signals are mapped 1-2 into symbols, then the symbols are converted from a serial path into parallel blocks with a series to parallel (S/P) converter 1-3 so a cyclic prefix 1-4 can be added to each block. A parallel to serial (P/S) converter 1-5 recombines these blocks into a serial link which is zero padded and filtered 1-6. A digital to analog (D/A) converter 1-7 converts the digital serial link to an analog signal and presented to an analog transmitter 1-8. The signal is sent over the wireless channel 1-9 which time disperses the signal and introduces noise 1-21 into the signal. A receiver front end 1-10 receives the distorted wireless signal and converted to a digital signal with an analog to digital (A/D) converter 1-11. The signal is then filtered 1-12. The prefix is removed 1-13 and a S/P converter 1-14 generates a time domain of parallel block signals that are applied to a time domain equalizer (TDE) 1-22 in the time domain. The time domain representation of the signal is sent to a de-mapper unit 1-18 after which the signal is applied to a P/S converter 1-19. The output signal is applied to the remainder of the baseband circuitry of the receiver to extract the signals from the transmitter. The TDE contained within the dotted box 1-22 and will be described in more detail shortly.